CVCBLR's VoW blog - Verification on the Web!

  With one of our recent blog entries on SystemVerilog constraint solver ( http://www.cvcblr.com/blog/?p=725 ) becoming so popular, several readers have contacted us via email to know little more about the puzzle. Specifically they wanted to understand how the solver ordering of variables is determined. Consider the same example as in that previous blog entry: As noted in the previous blog, this creates an “implicit ordering” of variables – i.e. ‘v1” is solved BEFORE “v2”. A smart engineer ( Muthurasu Sivaramakrishnan ) asked this: Nice one. However, why cant we use Solve.. Before constraint in this scenario? The answer is a little involved with yet-another subtlety in the language, and hence this new entry: This reader’s question boils down to whether the above constraint “ cst_ordered” is same as the following; constraint cst_guidance {solve v1 before v2;} First intuition says YES, but the answer unfortunately is NO. In SV there are 2 kinds of solver orde...

As the SVA usage expands/grows in the industry, so do the language syntax/features. One of the recent (2009) addition to System Verilog language was the ability to code “default disabling condition”. It is very handy to have an “inferred” disabling condition for all assertions so that one can save on verbosity while typing – every assertion doesn’t have to repeat;   a_without_default_disable : assert property (disable iff (!rst_n) my_prop); vs. a_with_default_disable : assert property (my_prop); Obviously anything that helps to save some typing is a BOON. However there are some special category of assertions that may get unintentionally disabled by this. For instance the “reset-checks” – assertions that check the reset value of various DUT outputs. For e.g. FIFO empty flag during reset serialout signal from a de-serializer design We recently had a similar DUT being verified with SVA. In the below code, notice the “default disable” and the reset-check...

Are you an avid fan of CRV – Constraint Random Verification? Have you played enough with System Verilog constraints? Many of our customers having attended our regular VSV training ( http://www.cvcblr.com/trainings ) do become so! One of the nice features of SystemVerilog constraint mechanism is its “bi-directionality” – a key feature that makes the distribution fairly wide spread and makes the state space well covered. The industry has learnt it over the last decade of CRV usage – bidirectional constraints are better than unidirectional ones (that was the default in previous generation solver inside popular tool like Specman – called PGen. Even Specman has moved to a more robust, bi-directional IGEN/Intelligen few years back). In SV this bi-directionality is subtle. Consider the code below: To an average SV engineer the above 2 constraints look “same” as the function is trivially doing a return job. However they are different for an avid SV user or a solid SV solver such as...

  Over the past few years, the term “pre-silicon verification” has been quite popular and several technology advancements have helped in solving that puzzle. Some of the biggest contributors have been languages such as e /Specman and SystemVerilog with supporting technologies such as constrained-random verification (CRV), coverage-driven verification (CDV) and assertion-based verification (ABV). All these three technologies when used in unison addressed the challenge at the block or intellectual property (IP)level fairly well. Recently UVM has been developed as a framework to use these languages in the best possible manner to try and keep these technologies scalable to larger designs, such as system-on-chips (SoC). Thanks to the Accellera committee devoting time and effort, UVM is becoming quite popular and the de-facto IP verification approach. However with SoCs, there are several new challenges in the verification space that threaten to quickly outgrow the current prevalent t...

Recently a UVM user pondered over the following question: randomization NOT happening for seq_item variable if uvm_field_* is NOT enabled? ( http://goo.gl/TNSaz ) To appreciate the issue, consider the code snippet as below: Since both hdr and pkt_len are declared rand, one expects them to be randomized. Note that one of the `uvm_field_int is commented – to demo the issue. Now a recipient/consumer of this transaction does a copy/clone at destination. See a code snippet: So far so good, let’s see what happens in a typical Questa simulation: The above results of hdr being NOT generated occurs consistently for all seeds (See the forum post if needed). So a typical user suspects that the missing uvm_field_int macro does control the randomization – though not intuitive/true. This could consume quite a few debug cycles (recall that the macro above is commented for demo only, in actual work, as reported in that forum posting, user forgot to  add that at the ...

Recently a user sought to assign a 4-state array (declared as logic ) from the DUT side to a 2-state, bit typed array on TB side. Quite normal and intelligent choice of datatype – as all the TB components at higher level should work on abstract models. However there are 2 important notes – one on the “syntax/semantic” and other on real functional aspect. Focusing on the functional aspect first (as the semantic would be caught by the compiler anyway), what if the DUT signal contained X/Z on the 4-state array value?       When you assign it to the 2-state array counterpart on the TB side – there is information loss and potentially wrong data :-(   Here is where a simple assertion could save hours of debug time for you. Recall that SV has a handy system-function to detect unknown values. One could write a simple assertion using that function at the DUT-TB boundary. See the full code below, with the assertion part highlighted:   With the SVA inc...

  As many of our readers would recall, CVC first became very visible to the industry with our early contribution to the assertion-based verification (ABV) via IEEE-1850 PSL (Property Specification Language). Back in 2004 we co-authored our first book on this wonderful language, first of its kind in the temporal assertion languages to become a standard ( See our timeline in Facebook for more ). Since then it has been a wonderful run of events in this world of functional verification for close to a decade by now. One of the significant features of PSL has been its simplicity and succinct means of expressing complex temporals through its “Foundation Language” (a.k.a LTL style) subset. We talk about this in detail in our PSL book ( http://www.systemverilog.us/psl_info.html ). Recently a user came up with a nice requirement at Forum in Verification Academy (See: http://bit.ly/14JTHlI) The spec goes as follows: The user attempted a simple SVA 2005 style, but got weird results...