As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does! For those yet to get there – here is a quick recap: Simple inheritance Few derived classes One can of-course “derive” from another “derived class” too, as-in: This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular UVM training sessions ( http://www.cvcblr.com/trainings ) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.). However what was not allowed in older SystemVerilog (2005/2009) is: Multiple inheritance, as in:...
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