SystemVerilog code automation from Puneet

Good news for all those Emacs + SystemVerilog users. Puneet has just now released his SV Snippet for Emacs, see:

http://coverification.org/2009/12/17/systemverilog-snippets-for-emacs/

Will certainly try it out ASAP. Good start Puneet, keep it up. Thanks for sharing it!

Comments

Post a Comment

Popular posts from this blog

Did you miss multiple-inheritance in SystemVerilog?

Image
As some of our customers ask during our advanced SystemVerilog/UVM training sessions, SystemVerilog doesn’t allow multiple-inheritance. Or to be precise “DID NOT have”, now in SV-2012/2013 it does! For those yet to get there – here is  a quick recap:     Simple inheritance                  Few derived classes             One can of-course “derive” from another “derived class” too, as-in:   This is used widely in good System Verilog code and in general any OOP code. UVM uses this a lot as many of you who have been fortunate to have attended our popular UVM training sessions ( http://www.cvcblr.com/trainings ) across the world (Yes, we have delivered across India, various cities, across the globe as in Europe, Asia etc.). However what was not allowed in older SystemVerilog (2005/2009) is: Multiple inheritance, as in:...
Read more

Verilog subtleties - $monitor vs. $display vs. $strobe

Image
Last week, our good friend Gaurav Jalan wrote a nice blog at: http://whatisverification.blogspot.in/2012/08/laws-and-verification.html   He has adapted Murphy’s law into Verification as: Applying to Verification ( http://whatisverification.blogspot.in/2012/08/laws-and-verification.html ) Moore’s law – Amount of code to be verified doubles every 2 years. Murphy’s law – Any code that isn’t verified will not work. Now as I recap on last week’s Verilog session delivered to an excited IIT-KGP audience, I realized the same law is applicable to slides/PPT/training too :-) Especially be careful with any code snippet shown in the slides – they  could be wrong – unless verified otherwise ! Now back to the title of this blog entry – what are the differences bet’n Verilog’s $display, $monitor & $strobe ? 1. Usual answer: $monitor is “continuous monitoring” – Yes, good For many fresh graduates the detail stops there – but not for those “verilog hungry, pedanti...
Read more

Do you care for better error messaging in SystemVerilog compiler?

Image
With so much fever around SystemVerilog in the verification community, more and more junior engineers are picking up System Verilog. Infact several universities started teaching System Verilog as part of advanced VLSI degree. And with its availability in Desktop based simulators like FPGA design tool chain, more and more FPGA designers are looking at it, and adopting it rapidly. Clearly SystemVerilog with its all gun blazing features are useful for FPGA community at large, our CTO Srini presented this at FPGA Camp in Bangalore few years ago: http://www.slideshare.net/mobile/fpgacentral/upgrading-to-system-verilog-for-fpga-designs-srinivasan-venkataramanan-cvc   Since then we have trained several FPGA teams on using: SystemVerilog for Design (SVD: http://www.cvcblr.com/trng_profiles/CVC_LG_SVD_profile.pdf ) SystemVerilog Assertions: (SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf ) VSV: ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ) ...
Read more