What are your painpoints with SystemVerilog ABV adoption?

While there is so much talk about ABV in the market, the adoption is still far less than desired/expected by the buzz! Harry Foster from Mentor tries to find some rationale in his new blog at:

http://blogs.mentor.com/verificationhorizons/blog/2009/12/06/abv-and-people-from-missouri/#comment-6

 

Here is what we from CVC feel about it (also added as comments in that blog).

>> What are the obstacles you see to adoption?

Major one I hear from RTL folks often is the verbosity associated (as of SystemVerilog 2005) with using OVL-like libraries. Especially existing users of 0-in checkerware are so much pampered by the ease of use and the value it adds - though their management may have the extra $$ as concern - it is hard for them to appreciate the need to type-type-type the “clock, reset” mundane stuff! It was all being “inferred” so far and suddenly come a standard language/implementation such as SVA and that takes them back in history! Refer to AMD’s excellent presentation on OVL TC for a proof! True, the new (very new I must say) “checker” construct along with $inferred* takes care of it (sigh… it lacks $inferred_enable). We cover these in our recently published SVA Handbook 2nd edition (http://www.systemverilog.us/sva_info.html) and also in upcoming DVCon 2010 paper.

Cheers
Srini
http://www.cvcblr.com

 

What do you have to say? Please comment, your views will hopefully help in shaping up future SystemVerilog standard!

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