Introducing “totally vacuous” assertion attempts

See our interesting Blog post at: http://www.vmmcentral.org/vmartialarts/?p=1130 

On the topic of adding SystemVerilog “bind files” – a new tool that is shaping up can help automate even that part – see ZazzOVL (www.zocalo-tech.com). Though as of now it works only for OVL, technically speaking it is very easy to extend it for user specified assertion libraries/modules/MIPs etc.

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