Creating quality Verification engineers for VLSI ecosystem

Here is the tale of Mr. Avit Kori, who recently finished his 2-month advanced Verification course @ CVC (www.cvcblr.com/trainings). He possessed strong design skills with Verilog/VHDL but was finding it hard to scale upto modern day VLSI job requirements before joining CVC. At CVC not only did he learn technologies such as

VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf

SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

VMM: http://www.cvcblr.com/trng_profiles/CVC_DR_VMM_profile.pdf

He also contributed to our OVM inhouse project creating quality code, testplan etc. It is that project experience that provided true differentiator in excelling and getting the right breakthrough!

We, TeamCVC wish him all the very best in his future endeavors.  Here is what Avit had to say about our TeamCVC:
Hi Team CVC,

Today I am very pleased to inform you that I got an opportunity to join Perfectus Technology as a Verification Engineer.

My sincerest thanks to the Team CVC for training and guiding me. I am really proud that I got the opportunity to be trained under Srini sir and Ajeetha mam. Again Anand, Prabu and Jijo always looked forward to solve my doubts. Without all of this I would never have been able to achieve the level of confidence required to become a good verification engineer.

I really appreciate all your efforts for giving me have such a memorable experience at CVC.

Thanks and Regards.

Avit Kori

http://in.linkedin.com/pub/avit-kori/1b/6/ba3

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