CVC's SystemVerilog training rocks! Read customer recommendation

From: http://in.linkedin.com/in/cvcblr


Smitha from Altera US (San Francisco http://www.linkedin.com/pub/smitha-kaginele/8/351/652 ) recently attended our VSV + SVA + VMM package for 4-weeks. Here are some of the reflections in her own words:






“I attended SystemVerilog, SVA and VMM training in CVC Pvt Ltd and had a great learning experience. The best part of the training was the live discussions on the verification "Gotchas" that are not addressed in manuals or books. These exhaustive discussions helped me understand the powerful features of the language and explore the verification concepts in-depth. The instructors are very well qualified, dedicated and passionate about their training program and have designed it to deliver the best. The CVC team is very friendly and are always there to help out with any lab issues. I would like to thank Ajeeta and Srini for the excellent work.” September 10, 2010


Top qualities: Great Results, Personable, Expert



Smitha Kaginele
hired TeamCVC as a Training Institute in 2010


For your reference,  course details at:


VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf



SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf

VMM: http://www.cvcblr.com/trng_profiles/CVC_DR_VMM_profile.pdf

Comments

Post a Comment

Popular posts from this blog

Easier PLI integration with MPSim

Image
Several engineers working and aspiring to work in the field of ASIC front-end design/verification tend to stay away from Verilog’s powerful PLI/VPI – some of them because they see it as old technology and many others – simply “FEAR” from it, thanks to its complex integration with the tools. For those who believe it is old technology – think again, most of the cutting edge EDA innovations (in front end) happening around verification use Verilog’s PLI/VPI to talk to your underlying simulator. To quote a few examples: NextOp /Atrenta’s BugScope   Novas’s Verdi/Debussy Axiom’s @Designer http://www.axiom-da.com (Debugger that can work with all standard Verilog simulators) Trek from Brekersystems ( www.brekersystems.com ) OnPoint from vennsa-da.com Now for those who “fear” from VPI due to its integration challenges – to be fair – you’ve reasons to do so. However advanced functional verification solutions such as VCS, MPSim ( http://www.axiom-da.com ) provide a...
Read more

SystemVerilog Soft constraints usage in `uvm_do_with macro

Image
Recently we were asked a good & interesting question: How do I use "soft constraint" in the macro `uvm_do_with? What would be the syntax? I say this is a good & interesting b'cos of 2 things: 1. The SV LRM doesn't give an explicit example for this (it is fine, not that it should, LRM is not a textbook) 2. The use case should be considered (This specific user had a good need - for automatic coverage closure - or ACC). Now quickly jumping to solution, based on our SystemVerilog 2012 tutorial that our CEO Ajeetha delivered at IIT Mumbai earlier in 2014 ( http://on.fb.me/1yfcBSx ), here is a code snippet: For those who need a quick background on what are soft constraints , see: http://www.cvcblr.com/blog/?p=629   Now with 3 major EDA vendors supporting this syntax, you should leverage on this more!
Read more

Smart one-liner for bit inversion in SystemVerilog

Recently one of CVC’s successful alumni, Harshal posted a nice challenge for SystemVerilog newcomers. Harshal has gone through our time trusted, long term SystemVerilog course and got placed at Synopsys and his career has been growing ever since. The original post describing the background is at: http://goo.gl/oq4FmF Crux of it was to “reverse the ordering” or change endianness of a bit stream. While a really rudimentary approach would be to do bit-by-bit as in:   bit [7:0] msb_vec, lsb_vec; msb_vec[7] = lsb_vec[0]; msb_vec[6] = lsb_vec[1]; // … While the above works, it is hard to maintain, upgrade for larger sizes etc. He attempted to automate it using Verilog (V2K)’s bit-slicing as in:   msb_vec [(28-i)] = lsb_vec[(0+(i))-:1]; //Bit Slicing logic But hold on, there is even a smarter way in SystemVerilog, use the “bit streaming” operator: $display (" msb_vec: %b reverse: %b", msb_vec, { << {msb_vec} } ); If the array was unppacked, there is a built-in array.reverse() ...
Read more