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Showing posts from September, 2011

Want to contribute/drive IEEE standards from India? Join this free Webinar to learn how!

Join IEEE-DASC webinar for free at: https://www1.gotomeeting.com/register/450027193   It is often a dream for many engineers in India to be part of IEEE committees, groups & associations and most of us feel proud about it. Here is your opportunity to take this to next step – you could well be developing, participating in next generation standards with special focus on India specific requirements too. Learn all about what it takes to participate in these activities in this hour long webinar for free @ https://www1.gotomeeting.com/register/450027193 Title: IEEE Design Automation Standards in India Date: Tuesday, September 27, 2011 Time: 8:00 PM - 9:00 PM IST For instance in the VLSI/EDA field there are several active standards such as: •IEEE 1800 – SystemVerilog •SV-AC assertions •SV-EC – enhancements/TB •Accellera VIP TSC – UVM •IEEE 1647 – E language •IEEE 1800 – PSL •IEEE 1076 – VHDL •IEEE 1801 UPF/Low Power •IEEE 1666 SystemC