Using SystemVerilog Assertions to check clock inversion

A while ago, a user asked :

I am trying to check that one of the my inverse clk is reverse of sys_clk:

I have written assertions , but when I am seeing this its checking only on falling edge of sys clk !
Please advise
property me;
@(clk)
clk |-> ~clk_inverse;
endproperty
inverse_pp: assert property (me)
else
$error ("inverse clk is not inverse as expected", $time);

 

Here comes the “deferred assertions” to your rescue – a new feature in SVA 2009 LRM.

ap_check_inv_clk : assert #0 (clk == !inv_clk);

Can be used both inside a procedural block (such as always_comb) or outisde (as a concurrent statement).

 

Try and let us know if it worked for you – BTW, don’t forget to turn SV 2009 flag ON to your SV tool to compile the above!

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