Raise a few eyebrows with SVA’s $rose

Assertions have always been our passion at CVC. The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late.

In one of our recent, part-time SVA training session (http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions:

"Things look bright when SVA syntax is discussed. it gets better when we start discussions"

One of the nice features in SVA in the ability to detect rising edge with $rose. It is quite simple to understand when applied on single bit signal. For non-startes, it is simply a change from 0 to 1. That's true for a single bit. What about vectors? In the below code, consider “addr” signal as 4-bit vector (logic [3:0] addr;)

If you thought it is 0 to 1 as in decimal, you are straightaway in for a surprise. If you suspect it is “bitwise” ORing of all bits – you are over-thinking on this. Consider the trace below along with SVA result (with Cadence’s IUS & nice Simvision GUI)

 

rose2

Consider an example of 4-bit vector  and few transitions.

rose6

That’s the change of LSB from 0 to 1 is really $rose.

Now consider the below transitions:

rose5

i.e. not every other bit counts here – only the change in LSB is considered. Did that raise an “eyebrow”?

Now consider an ascending order of “addr” values: (0 –>1 –> 2 -> 3 –> 4..)

image

Note that every alternate transition causes the $rose to be true, indicated by the “failed” notification in Simivision above - recall the system verilog assertion as:

$rose (addr) |-> 1’b0; // flag a failure, make it visible

Make no mistake, the $rose doesn’t work on “strictly ascending” consider few more traces below:

rose7

Now to raise few more eyebrows, consider the below trace with “descending” series of addr values:

image

So while a simplistic view of “0 to 1” is “ascending/increment”, the $rose is different when it is applied on a vector, even “descending/decrementing” transitions trigger $rose.

Now to summarize: $rose –> EVEN to ODD change :-)

Want to learn more SVA tricks, drop us a note via training@cvcblr.com to know about our next SVA training session in Bangalore.

Signing off,

TeamCVC 

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