CVCBLR's VoW blog - Verification on the Web!

ASIC Design-Verification lead (DVL-08-01) Job code: DVL-08-01 Exp: 4-8 years Note: there are also individual contributor roles. Summary of skills needed: - Advanced verification methodologies, preferably SystemVerilog - including testbench development - (G)DDR2/3 verification experience - Good problem solving, teamwork Send CV to career@cvcblr.com ---------- As an ASIC Verification engineer at high end semiconductor design house, verify the design and implementation of the industry's leading Graphics and Video Processors. Specific areas include 2D and 3D graphics, mpeg, video, audio, high-speed IO interfaces and bus protocols, and memory subsystem design. In this position, you will be responsible for verification of the ASIC design – architecture and micro-architecture - and it may include pre-silicon, emulation, and post-silicon activities. You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verif...

Here is the tale of Mr. Avit Kori, who recently finished his 2-month advanced Verification course @ CVC ( www.cvcblr.com/trainings ). He possessed strong design skills with Verilog/VHDL but was finding it hard to scale upto modern day VLSI job requirements before joining CVC. At CVC not only did he learn technologies such as VSV: http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf SVA: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf VMM: http://www.cvcblr.com/trng_profiles/CVC_DR_VMM_profile.pdf He also contributed to our OVM inhouse project creating quality code, testplan etc. It is that project experience that provided true differentiator in excelling and getting the right breakthrough! We, TeamCVC wish him all the very best in his future endeavors.  Here is what Avit had to say about our TeamCVC: Hi Team CVC, Today I am very pleased to inform you that I got an opportunity to join Perfectus Technology as a Verification Engineer. My sincerest thanks to the Team CVC f...

  Playing around debugging some complex assertions in Qeusta? Here are some tips:   1. Use vsim –assertdebug 2. Add –novopt for trivial code containing assertions + stim alone as otherwise many signals get optimized away. On real designs, perhaps you are better off with +acc* (Read doc for more) 3. Once the GUI comes up, the assertions are not listed in its own browser – ideally I would have liked to see a menu item under “Tools” menu. But it is hidden under “View –> Coverage –> Assertions” – GOK why! (GOK – God Only Knows) :-) 4. Before starting simulation, enable ATV 5. After sim one can do “view ATV” for advanced debug!  

Arayik Babayan, a friend of mine from Armenia asked me what is the use of “apply_config_settings” in OVM. As you may be aware SystemVerilog is a flexible language that can be used for building highly configurable and scalable verification environments. OVM adds a great deal of capabilities on top of plain “system verilog” to make it lot easier to handle that task. One of them is the configuration interface mechanism – usually we use set_config* and get_config* stuff. Internally OVM’s build() takes care of “applying” these settings. automatically usually. What if you want to change few settings across the env after the build? That’s when you use this apply_config_settings explicitly – it internally calls the set_*local for modified settings and viola – you are ready to go! That’s “advanced OVM” for this week!   Enjoy OVMing.. TeamCVC www.cvcblr.com/blog

… Tuesday Technote on Solver Debug, Jijo PS, Srini TeamCVC www.cvcblr.com Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time ever I look at this design/env as the original author moved out of the company (sign of good times :-) ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?). # Number of fware xactn 19 # ** Fatal: [Time 0 ns] Test cfg Solver failure #    Time: 0 ns  Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../ rt_test_03.sv Line: 83 # ** Note: Data structure takes 9699728 bytes of memory #          Process time 0.03 seconds #          $finish    : ../test/san_rt_test_03.sv(83) #    Time: 0 ns  Iteration: 2  Instance: /san_rt_top/san_rt_test_pgm_0 So what next? Consult our friendly Questa S...

…Reflections from core engineering team of CVC - fresh from SNUG India 2010 Jijo PS, Thirumalai Prabhu, Kumar Shivam, Avit Kori, Praveen & Nikhil – TeamCVC www.cvcblr.com 2010 has been a great year so far for us the verification community in India – with constant news of fresh hirings, new project starts etc. For us at CVC things have been as busy as we would like them to be – both from trainings and consulting perspective. Now that we have an army of VMM-aware engineers, we decided to let them see how the different product companies leverage on the matured methodology during SNUG India 2010, earlier this week. The results were amazing – every one of the attendees thanked us for letting them feel the vibrant VMM straight from the horse’s mouth – the real users, developers etc. Here is a quick collection of various VMM updates from SNUG India 2010 – as seen by TeamCVC. Expect to hear more on VMM1.2 soon from us as now I have a young team all charged up with VMM 1.2 (thanks to Amit @...

Recently Dr. M M Pallam Raju, Honorable Minister of State for Defense, Government of India, released ISA-Frost & Sullivan 2009-11 India Semiconductor Market Update. Here are excerpts from his speech during this release:   To face tomorrow, the Indian semiconductor industry has to rise to meet the challenges from other Asian countries and aid in developing the ecosystem. China and Vietnam are emerging as strong competitors in this industry. The Indian industry will have to address certain vital links in its ecosystem, such as systems engineering, venture capital and IP protection, to become more robust. It will also have to take measures to build up a skilled and technically trained, design-aware workforce for the future.   CVC is well poised to address this very challenge – both in terms of creating the workforce and delivering top-notch services to the industry. Look at our EIC: http://www.slideshare.net/svenka3/anubhuti-engineering-incubation...