CVCBLR's VoW blog - Verification on the Web!

One of the verification related constructs in the vast SystemVerilog language is the program construct. It is also one of the most debated features as to whether it is needed or not. Sure it is very well supported by all EDA tools, and heavily promoted by Synopsys with their VMM to start with. OVM (from Mentor & Cadence) didn’t advocate it though and in fact they discourage it. With UVM – it is a 50-50 – if you like it, use it, else don’t bother. From a technical perspective we at CVC like the fact that we now have a clear TB-2-DUT separation. We do teach this during our regular VSV training sessions ( http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf ). Here comes a 2-minute run-down on this nice feature. Let’s look at some code:   Line 6: #10 DUT ‘reads” a signal named “sig_1”. Line 14: #10 TB “drives” the same signal “sig_1” (They are connected, not shown above) Consider that the above “write” and “read” to the signal were done on “module” scope – t...

Assertions have always been our passion at CVC . The huge marketing buzz around UVM has some impact on how SVA was adopted and talked about at customer sites over last few years. Now that UVM is stable and getting well adopted, users are realizing that assertions play a key role in a UVM env as high quality checkers that can find bugs close to the source of occurrence. Specifically we see more user queries on SVA and training requests on SVA has been on the raise off-late. In one of our recent, part-time SVA training session ( http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf) we had a nice discussion on $rose with a set of enthusiastic attendees. Here is our favorite saying on Assertions: "Things look bright when SVA syntax is discussed. it gets better when we start discussions" One of the nice features in SVA in the ability to detect rising edge with $rose . It is quite simple to understand when applied on single bit signal. For non-startes, it is simp...

As part of my recent DAC 2013 minutes, here are some of the musings from customer experiences around DAC this year (and some from projects we have been doing in 2012-13 here). While there is a large set of customers exploring SystemVerilog in its full capacity and with UVM, make no mistake - not many will throw away what has been done previously and that was precisely my talking point at DAC 2013 theater presentation earlier this June. Below are some of the slides I presented to get you started: And it is in this context the recently announced UVM-ML initiative from Accellera http://www.accellera.org/apps/org/workgroup/mlwg/ becomes very relevant to every verification team. It is still very much open and all of you can contribute to developing this to be useful to the verification community at large. You can learn more about this UVM-ML from this Cadence blog:  http://bit.ly/14IdjrA See you soon at UVM-ML conference calls/discussions. TeamCVC

As I recount on my recent DAC at Austin experince, one thing that surprised me was the number of Giraffes (sure, images/toys, wish the real ones..but I was at DAC and not a zoo/safari) in the exhibit floor.   Yes, am talking about the Verific's mascot here. It was one of the tallest standing booths so not many could miss it. My friend Sashi Oblisetty led me to them after our early breakfast meeting that morning at DAC. I met with Michiel Ligthart, Verific’s president and chief operating officer. He is a tall man, a Netherlander/Dutch (Graag, ik kan een klien beetje Nederlands spreken .. -  Glad, I can speak a little bit Dutch language, thanks to my early days of work at Philips, Eindhoven). It was a pleasant surprise to see how many customers Verific has to-date, from their facebook page I found: That's impressive indeed. No wonder I found several small Giraffes on other vendors' booth tables. It reminded me of the popular "Intel inside" campaign, perhaps Verific ...

It surprises me often how many young engineers (read "fresh graduates/Recent College Graduates") struggle when it comes to the UNIX/GCC/Makefiles etc. I still recall our old IIT days when we did Yahoo/Altavista (Google wasn't around back in 1996) search to resolve most of such issues and of-course use some common sense.  Coming to the recent experience, as we were preparing for our recent demo at SNUG India 2013 DCE booth, I asked some of our young team members to run few UVM tests. When it came to the 11th hour preparations I got several error reports from these young engineers with various errors related to gcc/PATH etc. In our regular UVM training sessions the Makefiles exist so not much challenge in this regard. But when you ask these folks to create Makefile on their own to run UVM, things start getting interesting. A recent error message showed to me was:   recompiling module apb_subsystem_top All of 30 modules done  g++ -w -pipe -O -I/home/student/tools/eda/synops...

SystemVerilog enhances the TEXT-MACRO feature (a.k.a `define-s by many young engineers) of Verilog by a good length. Significant enhancements done are: Added capability to extend the definition to multiple lines Added macros with arguments; Macro arguments can have default values too! (not fully supported by all tools though) However there are few caveats – in general any text-macro usage in any computer language is hard to debug when it fails to compile. So be ready to be patient while debugging macro code. Recently an online forum user asked a question on SystemVerilog macros. Here is what the user defined to start with: To a bare eye, the above looks fine. However a  SV compiler would through an error at it. As per the LRM:   If formal arguments are used, the list of formal argument names shall be enclosed in parentheses following the name of the macro. The left parenthesis shall follow the text macro name immediately, with no space in ...

With SystemVerilog language gaining popularity among user, it is getting interesting to see user asking similar/repeating “patterns” of challenges in various forums. One of them is on constraint modeling when it becomes more than simple “a > 10” like stuff. Recently a VerifAcademy user asked:   in my testbench i have to make a random signal "[31:0] distortion". it must contain one (or, in other case, two) hot bit(s) (hot bit is "1", all others are "0"). So i have a problem with writing a constraint: i really don't want to write all possible combinations of these bits (if there are two of them, there will be 32! combinations, so...). Does anyone have solution for this problem?   A smart model is indeed available via 2 features of this vast language – System Verilog: 1. A handy system function to count the number of “ones” 2. Constraints can use functions in expressions. Combining the above two, here is a full solution to the ab...