CVCBLR's VoW blog - Verification on the Web!

Recently Amit (Yet another successful VLSI engineer from CVC’s incubation http://www.cvcblr.com/trng_profiles/CVC_EIC_profile.pdf , asked this: In OVM/UVM ( http://www.cvcblr.com/trng_profiles/Do-it-Right-UVM.pdf ) I am little confused about the way components are hooked-up hierarchically. Consider the code below: In the above constructor ,sometimes I am writing parent =null and some times only parent ,and then passing in super.new();, blindly i am doing this ,but i am not understanding why i am making parent=null and sometime leaving this as parent . what will be the effect of making so. kindly help me. Answer/Explanation: As an enhancement to Verilog, System Verilog allows “default values” for function/task (methods) arguments. By doing so it allows the caller of these methods to have the flexibility in number of arguments – a.k.a variable arguments to a function (though not overloading as in VHDL). So in the example above, the new has 2 arguments, both ha...

A while ago, a user asked : I am trying to check that one of the my inverse clk is reverse of sys_clk: I have written assertions , but when I am seeing this its checking only on falling edge of sys clk ! Please advise property me; @(clk) clk |-> ~clk_inverse; endproperty inverse_pp: assert property (me) else $error ("inverse clk is not inverse as expected", $time);   Here comes the “deferred assertions” to your rescue – a new feature in SVA 2009 LRM. ap_check_inv_clk : assert #0 (clk == !inv_clk); Can be used both inside a procedural block (such as always_comb) or outisde (as a concurrent statement).   Try and let us know if it worked for you – BTW, don’t forget to turn SV 2009 flag ON to your SV tool to compile the above!

As Indian VLSI industry is hiring at crazy rate for verification, SystemVerilog has emerged as a key differentiator in most of the front-end Verification job roles (see: http://www.linkedin.com/groups?homeNewMember=&gid=3706843 ). With many engineers adding SV skills to their CVs – the interviewers are getting tougher and smarter in their questions during interviews. Some related to OOP are below, source: http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4410 As our CEO posted some code snippet to start with  -we thought we will assist our junior engineers to ponder around the same and explore more on this topic. class base_pkt;   bit b1;   virtual function void display;     $display ("base_pkt: b1: %b", this.b1);   endfunction : display endclass : base_pkt class extended_pkt extends base_pkt;   bit b2;   virtual function void display;   ...

  Here is a recent posting that TeamCVC did on Facebook group ( http://www.facebook.com/groups/199014503449605/ ) , thought it is worth sharing it widely. Bottomline – if you are interested in VLSI, there is nothing that stops you from doing it for free even at college level!   When you say "tools" - a full ASIC platform for free is not realistic, unless it is academic - in which case look at Alliance: http://sourceforge.net/projects/alliancecad/ Though some of the tools in Alliance are industry ready, usually students in India have better tools at their disposal (just that they don't know about it). For instance: Modelsim Student edition http://model.com/content/modelsim-pe-student-edition-hdl-simulation Riviera-Pro student edition: http://www.aldec.com/en/products/university_programs These tools will run on Windows and or Linux. One can install Cygwin ( www.cygwin.com ) and get Linux-like experience on Windows itself (to be ready for industry). Af...

In the midst of a cold winter across India, there is some good news for those SystemC enthusiasts. While some in the industry thought the SystemC is being slow in adoption, there has been a constant need for moving up in abstraction in designing electronic systems. Over the past several years several ESL experiments have been carried out by local semiconductor/system companies in India. Incase you are deeply involved in this silent storm, here is your opportunity to broadcast your work as part of The Indian SystemC User’s Group (ISCUG). Abstracts are due by mid-Feb. See details at: www.iscug.in and you may download the CFP (Call For Papers from: http://www.cvcblr.com/downloads/iscug_CallForContribution.pdf See you at ISCUG!

Many users find the factory feature in UVM as quite satisfying and easy to use and believe callbacks are not needed in UVM. However callback is a popular design pattern in software domain (see: http://stackoverflow.com/questions/946834/is-there-a-design-pattern-that-deals-with-callback-mechanism ). It is infact one of the very nice things that came from VMM to UVM. Though it is not that often used in UVM as in VMM, there are some pertinent use cases that makes the callbacks very handy in UVM as well. For instance consider a recent customer requirement that we handled: How to terminate Testcase on Max Error Count Reached? Of-course UVM has this support, but little “hidden” (see http://www.cvcblr.com/blog/?p=203 for similar stuff on VMM). You use the function: set_report_max_quit_count(2); // Quit after 2 errors However in the context of “phasing” this “terminates/interrupts” the phasing rather “abruptly”. While the UVM developers believe this is fine as default behavi...

I am sure you have heard this phrase before – “A sledgehammer to crack a nut”; the below picture describes it all! Would you use a HUGE hammer to crack a small, tiny nut? (If you are further interested in this phrase read: http://www.phrases.org.uk/meanings/sledgehammer-to-crack-a-nut.html ). I recently had a small design error introduced in a piece of  RTL as below: It is an interrupt masking logic, code snippet as below: Note the use of “ANDing” logic – simply, AND- mask with data to produce result .The subtlety in Verilog/System Verilog is that you have 2 seemingly similar operators for doing AND operation; The logical AND: && The bitwise AND: & Given the “loose” data type checking, assignment rules etc. one can get away by using either one of the above many-a-times. In the above case the user used: result = data && mask; With result being a vector the above is a “logical/design error” but usually a Verilog compiler would let this go through (as it is not a...